1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and particularly, to a semiconductor device and a method of manufacturing a semiconductor device, in which a semiconductor light receiving element configured to detect short-wavelength light, for example, an ultraviolet light, and a MOS transistor are formed on the same silicon substrate.
2. Description of the Related Art
There are various types of semiconductor light receiving elements. Among those semiconductor light receiving elements, a light receiving element formed on a silicon substrate is used in many applications. This is because, by forming an integrated circuit including a MOS transistor or the like and the light receiving element on the same substrate, a process from receiving light to processing a signal can be conducted on one chip.
A penetration depth of light in silicon (a depth at which an intensity of the incident light to the silicon is attenuated to 1/e due to absorption) has a wavelength dependence, as shown in FIG. 7. Thus, in a case of an ultraviolet light (UVA: from 320 nm to 400 nm, and UVB: from 280 nm to 320 nm), most light is absorbed in a range of from several nanometers to several tens of nanometers. Structures for detecting the ultraviolet light using silicon, which has such features, are disclosed in Japanese Patent No. 5692880 and described in ITE Trans. on MTA Vol. 2 No. 2 pp. 123-130 (2014).
Specifically, in order to detect an electron-hole pair generated by irradiation of the ultraviolet light as a photocurrent, a depth of a pn junction is made shallow to be in a range from about several tens of nanometers to about several hundreds of nanometers. Further, having an impurity profile in which an impurity concentration in an outermost silicon surface is 1019 cm−3 or more and the concentration gradually decreases along a depth direction, generation of an electric field due to a concentration gradient causes effective separation of the electron-hole pair, permitting acquisition of the photocurrent.
In such a silicon light receiving element structure, when charges are trapped in an insulating film on silicon due to the irradiation of the ultraviolet light, a band structure of the pn junction may be affected such that sensitivity characteristic of the light receiving element fluctuates, as described in SPIE-IS&T/Vol. 8298 82980M-1-8 (2012). Accordingly the insulating film that is in contact with the silicon surface needs to be a thermal silicon oxide film having comparatively few charge traps. A high impurity concentration in the outermost silicon surface also has an advantage in that an influence of fixed charges in the insulating film is shielded.
Meanwhile, a related-art method involving forming an ultraviolet light receiving element including silicon and the MOS transistor together are disclosed in Japanese Patent Application Laid-open No. 2014-154793, for example. FIGS. 8A to 8D and FIGS. 9A to 9D are cross-sectional views for illustrating a manufacturing method of the related art in the order of steps. In FIGS. 8A to 8D and FIGS. 9A to 9D, PD represents a light receiving element forming region in which the light receiving element is formed, and TR represents a MOS transistor forming region in which a PMOS transistor is formed.
First, as illustrated in FIG. 8A, N-well regions 102 and an element isolation region 103 are formed on a surface of a p-type silicon substrate 101. Ion implantation for adjusting a threshold voltage of a transistor is performed as necessary, and then a gate oxide film 104 is formed through thermal oxidation.
Next, as illustrated in FIG. 8B, a polysilicon film 105, which is a material of a gate electrode, is deposited and patterned through etching such that a gate electrode 106 is formed (FIG. 8C).
Then, the light receiving element forming region PD is masked by a first photoresist film (not shown), ion implantation is performed on the MOS transistor forming region TR, to thereby form lightly doped drain (LDD) regions 109 (FIG. 8D).
The first photoresist film is removed, and then an insulating film 110 is deposited over the entire surface (FIG. 9A). The light receiving element forming region PD is masked by a second photoresist film (not shown) so as to prevent removal of the gate oxide film 104 in the light receiving element forming region PD, and anisotropic etching is performed. As a result, side walls 111 are formed on side surfaces of the gate electrode 106, and the gate oxide film 104 and the insulating film 110 remain in the light receiving element forming region PD (FIG. 9B).
Subsequently, ion implantation is performed on the MOS transistor forming region TR, to thereby form source/drain regions 112 (FIG. 9C).
Then, ion implantation for forming a shallow junction is performed on the light receiving element forming region PD, to thereby form an impurity region 108 (FIG. 9D).
As described above, according to the related-art manufacturing method, a MOS transistor and an ultraviolet light receiving element, which is formed from silicon and has a pn junction, can be formed together on the same silicon substrate.
In the related-art manufacturing method illustrated in FIGS. 8A to 8D and FIGS. 9A to 9D, the insulating film that is in direct contact with the surface of the silicon substrate in the light receiving element forming region PD is the gate oxide film 104 that remains after the patterning for forming the gate electrode. Hence, although the insulating film is a thermal oxide film, a quality of the insulating film may be deteriorated due to etching damage at the time of gate patterning. As described above, in order to suppress fluctuation in the sensitivity characteristics of the light receiving element, the insulating film that is in direct contact with the silicon surface needs to be a thermal silicon oxide film having comparatively few charge traps. Thus, the light receiving element in which the gate oxide film 104 having a deteriorated quality is in direct contact with the silicon surface has low reliability.
Further, the insulating film 110 that is deposited to form the side walls 111 is, in general, thicker than the gate oxide film 104 (for example, in Japanese Patent Application Laid-open No. 2014-154793, the gate oxide film has a thickness of from 10 nm to 50 nm, and the insulating film for the side walls has a thickness of from 200 nm to 500 nm). A high dose amount of more than 1016 cm−2 is thus needed in order to perform ion implantation on the light receiving element forming region PD through laminated films formed of the gate oxide film 104 and the insulating film 110 for the side walls, to thereby attain a desired concentration in the impurity region 108.
When ion implantation with this dose amount is performed at one time, failures, such as burning and sticking of a resist, may occur in the manufacturing process. Accordingly ion implantation is, in general, performed separately two times or more, which decreases a throughput. Further, since a junction depth becomes about 200 nm, a shallow junction of 100 nm or less, which is essentially needed to detect the ultraviolet light with high sensitivity, is not obtained. Still further, the impurity concentration of 1019 cm−3 or more is needed in the outermost silicon surface.